Renesas HD6417641 Hardware Manual page 329

Bit Bit Name
11 BLOCK
10 DPRTY1
9 DPRTY0
8 DMAIW2
7 DMAIW1
6 DMAIW0
Initial
Value R/W Description
0 R/W Bus Clock
Specifies whether or not the BREQ signal is received.
0: Receives BREQ.
1: Does not receive BREQ.
0 R/W DMA Burst Transfer Priority
0 R/W Specify the priority for a refresh request/bus
mastership request during DMA burst transfer.
00: Accepts a refresh request and bus mastership
01: Accepts a refresh request but does not accept a
10: Accepts neither a refresh request nor a bus
11: Reserved (setting prohibited)
0 R/W Wait states between access cycles when DMA single
address transfer is performed.
0 R/W
Specify the number of idle cycles to be inserted after
0 R/W
an access to an external device with DACK when DMA
single address transfer is performed. The method of
inserting idle cycles depends on the contents of
DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycled inserted
100: 6 idle cycled inserted
101: 8 idle cycle inserted
110: 10 idle cycles inserted
111: 12 idle cycled inserted
Section 12 Bus State Controller (BSC)
request during DMA burst transfer.
bus mastership request during DMA burst transfer.
mastership request during DMA burst transfer.
Rev. 4.00 Sep. 14, 2005 Page 279 of 982
REJ09B0023-0400