Renesas HD6417641 Hardware Manual page 208

Section 5 Watchdog Timer (WDT)
Bit Bit Name
4 WOVF
3 IOVF
2 CKS2
1 CKS1
0 CKS0
Rev. 4.00 Sep. 14, 2005 Page 158 of 982
REJ09B0023-0400
Initial
Value R/W Description
0 R/W Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
0 R/W Interval Timer Overflow
Indicates that the WTCNT has overflowed in interval
timer mode. This bit is not set in watchdog timer
mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
0 R/W Clock Select
0 R/W These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
0 R/W
peripheral clock (Pφ). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (Pφ) is 15 MHz.
Bits 2 to 0 Clock Ratio
000:
001:
010:
011:
100:
101:
110:
111:
Note: If bits CKS2 to CKS0 are modified when the
1
1/4
1/16
1/32
1/64
1/256
1/1024
1/4096
WDT is running, the up-count may not be
performed correctly. Ensure that these bits are
modified only when the WDT is not running.
In addition, the timing of the first overflow
includes deviation. See section 5.4,
Precautions to Take when Using the WDT.
Overflow Cycle
17 us
68 us
273 us
546 us
1.09 ms
4.36 ms
17.48 ms
69.91 ms