Figure 12.5 Continuous Access For Normal Space 2 Bus Width = 16 Bits, Longword Access, Csnwcr.wn Bit = 1 (Access Wait = 0, Cycle Wait = 0) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
Read
Write
Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 1
Rev. 4.00 Sep. 14, 2005 Page 326 of 982
REJ09B0023-0400
CKIO
A25 to A0
CSn
RD/WR
RD
D15 to D0
WEn
D15 to D0
BS
DACKn *
WAIT
The waveform for DACKn is when active low is specified.
*
Note:
Figure 12.5 Continuous Access for Normal Space 2
(Access Wait = 0, Cycle Wait = 0)
T1 T2 T1 T2