Table 23.8 Port G Data Register (Pgdr) Read/Write Operations (Pg13Dt To Pg11Dt, Pg8Dt); Table 23.9 Port G Data Register (Pgdr) Read/Write Operations (Pg10Dt To Pg9Dt); Table 23.10 Port G Data Register (Pgdr) Read/Write Operations (Pg7Dt To Pg0Dt) - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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Section 23 I/O Ports
Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13DT to PG11DT,
PG8DT)
PGnMD2 PGnMD1 Pin State
0
0
1
Other than above
(n = 8, 11 to 13)

Table 23.9 Port G Data Register (PGDR) Read/Write Operations (PG10DT to PG9DT)

PGnMD2 PGnMD1 Pin State
0
0
1
1
0
1
(n = 9, 10)

Table 23.10 Port G Data Register (PGDR) Read/Write Operations (PG7DT to PG0DT)

PGnMD2
Pin State
0
Input/other function
(The A/D converter is
used.)
Input/other function
(The A/D converter is
not used.)
1
Reserved
(n = 0 to 7)
Rev. 4.00 Sep. 14, 2005 Page 858 of 982
REJ09B0023-0400
Read
Input
Pin state
Output
PGDR value
Reserved
Read
Input
Pin state
Output
PGDR value
Reserved
Other function Pin state
Read
Prohibited
Pin state
Write
Data is written to PGDR, but does not affect
pin state.
Data is written to PGDR and the value is
output from the pin.
Write
Data is written to PGDR, but does not affect
pin state.
Data is written to PGDR and the value is
output from the pin.
Data is written to PGDR, but does not affect
pin state.
Write
Prohibited
Ignored (does not affect pin state.)

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