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Bit
Bit Name
12
SW1
11
SW0
10
WR3
9
WR2
8
WR1
7
WR0
6
WM
Initial
Value
R/W
Description
Number of Delay Cycles from Address, CSn Assertion
0
R/W
to RD, WE Assertion
0
R/W
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
1
R/W
Number of Read Access Wait Cycles
0
R/W
Specify the number of cycles that are necessary for
read access.
1
R/W
0000: No cycle
0
R/W
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Reserved (Setting prohibited)
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 291 of 982
REJ09B0023-0400
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