Section 10 Interrupt Controller (INTC)
Table 10.4 Correspondence between Interrupt Sources and IMCR0 to IMCR10
Register
Name
7
IMCR0
IRQ7
(IRQ)
IMCR1
TxI0
(SCIF0)
IMCR2
(ADC0)
IMCR4
—
—
IMCR5
TxI2
(SCIF2)
IMCR6
TCI2U
(MTU2)
IMCR7
—
(MTU0)
IMCR8
—
(MTU3)
IMCR9
—
(MTU4)
IMCR10
—
(CMT)
Note: : Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 232 of 982
REJ09B0023-0400
Bit Name (Function Name)
6
5
IRQ6
IRQ5
(IRQ)
(IRQ)
BRI0
RxI0
(SCIF0)
(SCIF0)
—
—
(ADC0)
(ADC0)
—
—
—
—
BRI2
RxI2
(SCIF2)
(SCIF2)
TCI2V
TGI2B
(MTU2)
(MTU2)
—
—
(MTU0)
(MTU0)
—
—
(MTU3)
(MTU3)
—
—
(MTU4)
(MTU4)
—
CMI1
(CMT)
(CMT)
4
3
IRQ4
IRQ3
(IRQ)
(IRQ)
ERI0
DEI3
(SCIF0)
(DMAC)
ADI0
TxI1
(ADC0)
(SCIF1)
—
ITI
—
(WDT)
ERI2
ADI1
(SCIF2)
(ADC1)
TGI2A
TCI1U
(MTU2)
(MTU1)
TCI0V
TGI0D
(MTU0)
(MTU0)
TCI3V
TGI3D
(MTU3)
(MTU3)
TCI4V
TGI4D
(MTU4)
(MTU4)
CMI0
IIC2I
(CMT)
(IIC2)
2
1
IRQ2
IRQ1
(IRQ)
(IRQ)
DEI2
DEI1
(DMAC)
(DMAC)
BRI1
RxI1
(SCIF1)
(SCIF1)
—
—
(WDT)
(WDT)
USIHP
USI1
(USB)
(USB)
TCI1V
TGI1B
(MTU1)
(MTU1)
TGI0C
TGI0B
(MTU0)
(MTU0)
TGI3C
TGI3B
(MTU3)
(MTU3)
TGI4C
TGI4B
(MTU4)
(MTU4)
—
—
(IIC2)
(POE)
0
IRQ0
(IRQ)
DEI0
(DMAC)
ERI1
(SCIF1)
—
(WDT)
USI0
(USB)
TGI1A
(MTU1)
TGI0A
(MTU0)
TGI3A
(MTU3)
TGI4A
(MTU4)
OEI
(POE)