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Section 2 CPU
Instruction
MOV.L
Rm,@(R0,Rn)
MOV.B
@(R0,Rm),Rn
MOV.W
@(R0,Rm),Rn
MOV.L
@(R0,Rm),Rn
MOV.B
R0,@(disp,GBR)
MOV.W
R0,@(disp,GBR)
MOV.L
R0,@(disp,GBR)
MOV.B
@(disp,GBR),R0
MOV.W
@(disp,GBR),R0
MOV.L
@(disp,GBR),R0
MOVA
@(disp,PC),R0
MOVT
Rn
SWAP.B Rm,Rn
SWAP.W Rm,Rn
XTRCT
Rm,Rn
Rev. 4.00 Sep. 14, 2005 Page 72 of 982
REJ09B0023-0400
Instruction Code
0000nnnnmmmm0110
0000nnnnmmmm1100
0000nnnnmmmm1101
0000nnnnmmmm1110
11000000dddddddd
11000001dddddddd
11000010dddddddd
11000100dddddddd
11000101dddddddd
11000110dddddddd
11000111dddddddd
0000nnnn00101001
0110nnnnmmmm1000
0110nnnnmmmm1001
0010nnnnmmmm1101
Operation
Rm → (R0 + Rn)
(R0 + Rm) → Sign extension
→ Rn
(R0 + Rm) → Sign extension
→ Rn
(R0 + Rm) → Rn
R0 → (disp + GBR)
R0 → (disp × 2 + GBR)
R0 → (disp × 4 + GBR)
(disp + GBR) → Sign
extension → R0
(disp × 2 + GBR) →
Sign extension → R0
(disp × 4 + GBR) → R0
disp × 4 + PC → R0
T → Rn
Rm → Swap lowest two
bytes → Rn
Rm → Swap two consecutive
words → Rn
Middle 32 bits of Rm and
Rn → Rn
Execution
States
T Bit
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
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