Figure 12.44 Burst Mpx Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
Tm1 Tmd1w Tmd1w
Tmd1
CKIO
FRAME
D31 to D0
A D
A25 to A0
CS6B
RD/WR
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.44 Burst MPX Space Access Timing
(Single Write, Software Wait 1, Hardware Wait 1)
Rev. 4.00 Sep. 14, 2005 Page 384 of 982
REJ09B0023-0400