Section 12 Bus State Controller (BSC)
A25 to A0
A12/A11*
RASL, RASU
CASL, CASU
D31 to D0
DACKn*
Figure 12.26 Single Write Timing (Bank Active, Different Bank)
Rev. 4.00 Sep. 14, 2005 Page 362 of 982
REJ09B0023-0400
Tr
CKIO
1
CSn
RD/WR
DQMxx
BS
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tc1