Figure 25.35 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: Write Command, Same Row Address, Wtrcd = 0 Cycle, Trwl = 0 Cycle) - Renesas HD6417641 Hardware Manual

CKIO
A25 to A0
1
A12/A11*
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
CKE
DACKn*
2
Note:
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle,
Tnop Tc1
t t
AD1 AD1
t t
AD1 AD1
t
CSD1
t t
RWD1 RWD1
t
CASD1
t
DQMD1
t t
WDD2 WDH2
t
BSD
t
DACD
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
TRWL = 0 Cycle)
Section 25 Electrical Characteristics
Tc2 Tc3 Tc4
t t
AD1 AD1
Column
address
Write command
t
WDD2
(High)
Rev. 4.00 Sep. 14, 2005 Page 947 of 982
t
AD1
t
AD1
t
CSD1
t
RWD1
t
CASD1
t
DQMD1
t
WDH2
t
BSD
t
DACD
REJ09B0023-0400