Noise Filter; Figure 16.17 Block Diagram Of Noise Filter - Renesas HD6417641 Hardware Manual

16.4.7

Noise Filter

The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 16.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When NF2CYC is set to 0, this signal is not passed forward
to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is
not passed forward to the next circuit unless the outputs of three latches agree. If they do not
agree, the previous value is held.
Sampling clock
SCL or SDA
D
input signal
Peripheral clock
Sampling
clock
C
C
Q D
Latch
Latch
cycle

Figure 16.17 Block Diagram of Noise Filter

C
Q
D Q
Latch
NF2CVC
Rev. 4.00 Sep. 14, 2005 Page 501 of 982
2
Section 16 I C Bus Interface 2 (IIC2)
Match
1
detector
Match
0
detector
REJ09B0023-0400
Internal
SCL or SDA
signal