Synchronous Dram Timing; Figure 25.23 Synchronous Dram Single Read Bus Cycle (Auto Precharge, Cas Latency 2, Wtrcd = 0 Cycle, Wtrp = 0 Cycle) - Renesas HD6417641 Hardware Manual

25.3.7

Synchronous DRAM Timing

CKIO
A25 to A0
1
A12/A11*
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
CKE
DACKn*
2
Figure 25.23 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
Tr Tc1
t t
AD1 AD1
Row
Column address
address
t t
AD1 AD1
ReadA
command
t
CSD1
t
RWD1
t t
RASD1 RASD1
t
CASD1
t
DQMD1
t
BSD
t
DACD
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Section 25 Electrical Characteristics
Tcw Td1 Tde
t
AD1
t
CSD1
t
CASD1
t
DQMD1
t
t
RDS2
RDH2
t
BSD
(High)
t
DACD
Rev. 4.00 Sep. 14, 2005 Page 935 of 982
t
AD1
t
RWD1
REJ09B0023-0400