Renesas HD6417641 Hardware Manual page 445

BSC Register Setting
CSnBCR CS3WCR.
Idle WTRP
Setting Setting
4 2
4 2
4 2
4 2
4 3
4 3
4 3
4 3
n (n>=6) 
Notes: The minimum number of idle cycles in CPU Access is described sequentially for Iφ:Bφ
(4:1/3:1/2:1/1:1).
1. DMAC is operated by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
CS3WCR.
TRWL Read to
Setting Read
0 5/5/5/5
1 5/5/5/5
2 5/5/5/5
3 5/5/5/5
0 5/5/5/5
1 5/5/5/5
2 5/5/5/5
3 5/5/5/5

All n+1
Section 12 Bus State Controller (BSC)
CPU Access
Write to Read to
Write Write
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
5/5/5/5 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
5/5/5/5 5/5/5/5
6/6/6/6 5/5/5/5
n/n/n/n All n+1
Rev. 4.00 Sep. 14, 2005 Page 395 of 982
DMAC Access
Write to Read to
Read Write
4/4/4/4 5
4/4/4/4 5
4/4/4/4 5
5/5/5/5 5
4/4/4/4 5
4/4/4/4 5
5/5/5/5 5
6/6/6/6 5
n/n/n/n n+1
REJ09B0023-0400
Write to
Read
4
4
4
5
4
4
5
6
n