Port B; Register Description; Figure 23.2 Port B; Table 23.1 Port A Data Register (Padr) Read/Write Operations - Renesas HD6417641 Hardware Manual

Table 23.1 Port A Data Register (PADR) Read/Write Operations

PAnMD2 PAnMD1 Pin Function
0 0
1
1 0
1
(n = 0 to 14)
23.2

Port B

Port B is a 9-bit input/output port with the pin configuration shown in figure 23.2. Each pin is
controlled by the port B control register (PBCR) in the PFC.
23.2.1

Register Description

Port B has the following register.
• Port B data register (PBDR)
Read
Input Pin state
Output PADR value

Reserved
Other functions Pin state
Port B

Figure 23.2 Port B

Write
Data is written to PADR, but does not affect
pin state.
Data is written to PADR and the value is
output from the pin.

Data is written to PADR, but does not affect
pin state.
PTB8 (input/output)/DPLS (input)
PTB7 (input/output)/DMNS (input)
PTB6 (input/output)/TXDPLS (output)
PTB5 (input/output)/TXDMNS (output)
PTB4 (input/output)/TXENL (output)
PTB3 (input/output)/XVDATA (input)
PTB2 (input/output)/SUSPND (output)
PTB1 (input/output)/VBUS (input)
PTB0 (input/output)/UCLK (input)
Rev. 4.00 Sep. 14, 2005 Page 845 of 982
Section 23 I/O Ports
REJ09B0023-0400