Figure 4.1 Block Diagram Of Clock Pulse Generator - Renesas HD6417641 Hardware Manual

Section 4 Clock Pulse Generator (CPG)
CKIO
CKIO2
Crystal
XTAL
oscillator
EXTAL
MD2
MD0
[Legend]
FRQCR: Frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
STBCR4: Standby control register 4
Rev. 4.00 Sep. 14, 2005 Page 144 of 982
REJ09B0023-0400
Clock pulse generator
PLL circuit 1
(×1, 2, 3, 4)
PLL circuit 2
(× 2,4)
CPG control unit
Clock frequency
control circuit
FRQCR
Internal bus

Figure 4.1 Block Diagram of Clock Pulse Generator

Divider
×1
×1/2
×1/3
×1/4
Standby control circuit
STBCR STBCR2
Bus interface
Internal clock
(Iφ)
Bus clock
(Bφ = CKIO)
Peripheral clock
(Pφ)
STBCR3 STBCR4