Figure 13.21 Example Of Dreq Input Detection In Cycle Steal Mode Level Detection When Dack Is Divided To 4 By Idle Cycles - Renesas HD6417641 Hardware Manual

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CKIO
Bus cycle
DREQ
(Overrun 1,
high-level)
DACK
(High-active)
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Rev. 4.00 Sep. 14, 2005 Page 448 of 982
REJ09B0023-0400
CPU
1st acceptance
Non-sensitive period
CPU
1st acceptance 2nd acceptance
Non-sensitive period Non-sensitive period
When DACK is Divided to 4 by Idle Cycles
DMAC write
2nd acceptance 3rd acceptance possible
Non-sensitive period
DMAC write
3rd acceptance possible