Table 18.40 Register Settings For Complementary Pwm Mode - Renesas HD6417641 Hardware Manual

Section 18 Multi-Function Timer Pulse Unit (MTU)

Table 18.40 Register Settings for Complementary PWM Mode

Channel Counter/Register
3 TCNT_3
TGRA_3
TGRB_3
TGRC_3
TGRD_3
4 TCNT_4
TGRA_4
TGRB_4
TGRC_4
TGRD_4
Timer dead time data register
(TDDR)
Timer cycle data register
(TCDR)
Timer cycle buffer register
(TCBR)
Subcounter (TCNTS)
Temporary register 1 (TEMP1)
Temporary register 2 (TEMP2)
Temporary register 3 (TEMP3)
Note: * Access can be enabled or disabled according to the setting of bit 0 (MTURWE) in
PTE/PEMTURWE (port E/port E MTU R/W enable register).
Rev. 4.00 Sep. 14, 2005 Page 592 of 982
REJ09B0023-0400
Description
Start of up-count from value set
in dead time register
Set TCNT_3 upper limit value
(1/2 carrier cycle + dead time)
PWM output 1 compare register
TGRA_3 buffer register
PWM output 1/TGRB_3 buffer
register
Up-count start, initialized to
H'0000
PWM output 2 compare register
PWM output 3 compare register
PWM output 2/TGRA_4 buffer
register
PWM output 3/TGRB_4 buffer
register
Set TCNT_4 and TCNT_3 offset
value (dead time value)
Set TCNT_4 upper limit value
(1/2 carrier cycle)
TCDR buffer register
Subcounter for dead time
generation
PWM output 1/TGRB_3
temporary register
PWM output 2/TGRA_4
temporary register
PWM output 3/TGRB_4
temporary register
Read/Write from CPU
Maskable by
PTE/PEMTURWE setting*
Maskable by
PTE/PEMTURWE setting*
Maskable by
PTE/PEMTURWE setting*
Always readable/writable
Always readable/writable
Maskable by
PTE/PEMTURWE setting*
Maskable by
PTE/PEMTURWE setting*
Maskable by
PTE/PEMTURWE setting*
Always readable/writable
Always readable/writable
Maskable by
PTE/PEMTURWE setting*
Maskable by
PTE/PEMTURWE setting*
Always readable/writable
Read-only
Not readable/writable
Not readable/writable
Not readable/writable