C Bus Control Register 2 (Iccr2) - Renesas HD6417641 Hardware Manual

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16.3.2 I

C Bus Control Register 2 (ICCR2)

ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in the control part of the I
Bit Bit Name
7 BBSY
6 SCP
5 SDAO
Initial
Value R/W Description
0 R/W Bus Busy
This bit enables to confirm whether the I
occupied or released and to issue start/stop conditions
in master mode. With the clocked synchronous serial
format, this bit has no meaning. With the I
this bit is set to 1 when the SDA level changes from
high to low under the condition of SCL = high, assuming
that the start condition has been issued. This bit is
cleared to 0 when the SDA level changes from low to
high under the condition of SCL = high, assuming that
the stop condition has been issued. Write 1 to BBSY
and 0 to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start condition.
Write 0 in BBSY and 0 in SCP to issue a stop condition.
1 W Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A retransmit start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1.
1 R/W SDA Output Value Control
This bit is used with SDAOP when modifying output
level of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
Section 16 I
(outputs high by external pull-up resistance).
Rev. 4.00 Sep. 14, 2005 Page 479 of 982
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C Bus Interface 2 (IIC2)
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C bus interface 2.
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C bus is
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C bus format,
REJ09B0023-0400