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Instruction
LDC.L @Rm+,
R4_BANK
LDC.L
@Rm+,
R5_BANK
LDC.L
@Rm+,
R6_BANK
LDC.L
@Rm+,
R7_BANK
LDS
Rm,MACH
LDS
Rm,MACL
LDS
Rm,PR
LDS.L
@Rm+,MACH
LDS.L
@Rm+,MACL
LDS.L
@Rm+,PR
NOP
PREF
@Rm
RTE
SETS
SETT
SLEEP
STC
SR,Rn
STC
GBR,Rn
STC
VBR,Rn
STC
SSR,Rn
STC
SPC,Rn
STC
R0_BANK,Rn
STC
R1_BANK,Rn
STC
R2_BANK,Rn
STC
R3_BANK,Rn
STC
R4_BANK,Rn
STC
R5_BANK,Rn
STC
R6_BANK,Rn
Instruction Code
0100mmmm11000111
0100mmmm11010111
0100mmmm11100111
0100mmmm11110111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000mmmm10000011
0000000000101011
0000000001011000
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0000nnnn00110010
0000nnnn01000010
0000nnnn10000010
0000nnnn10010010
0000nnnn10100010
0000nnnn10110010
0000nnnn11000010
0000nnnn11010010
0000nnnn11100010
Operation
(Rm) → R4_BANK,
Rm + 4 → Rm
(Rm) → R5_BANK,
Rm + 4 → Rm
(Rm) → R6_BANK,
Rm + 4 → Rm
(Rm) → R7_BANK,
Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
No operation
(Rm) → cache
Delayed branch,
SSR/SPC → SR/PC
1 → S
1 → T
Sleep
SR → Rn
GBR → Rn
VBR → Rn
SSR → Rn
SPC → Rn
R0_BANK→ Rn
R1_BANK→ Rn
R2_BANK→ Rn
R3_BANK→ Rn
R4_BANK→ Rn
R5_BANK→ Rn
R6_BANK→ Rn
Rev. 4.00 Sep. 14, 2005 Page 79 of 982
Section 2 CPU
Execution
States
T Bit
4
—
4
—
4
—
4
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
5
—
1
—
1
1
4*
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
REJ09B0023-0400
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