Figure 2.7 Dsp Registers; Figure 2.8 Connections Of Dsp Registers And Buses - Renesas HD6417641 Hardware Manual

39 32 31
A0G
A1G
31
Reset status
DSR: All zeros
Others: Undefined

Figure 2.7 DSP Registers

8 bits
MOVS.W,
MOVS.L
39 32
A0G
A1G
DSR
7 0

Figure 2.8 Connections of DSP Registers and Buses

A0
A1
M0
M1
X0
X1
Y0
Y1
(a) DSP Data Registers
8 7 6 5
GT Z N
(b) DSP Status Register (DSR)
16 bits
16 bits
MOVX.W MOVY.W
31
0
4 3 2 1 0
V CS [2:0] DC
LDB
XDB
YDB
32 bits
MOVS.W,
MOVS.L
16
0
A0
A1
M0
M1
X0
X1
Y0
Y1
Rev. 4.00 Sep. 14, 2005 Page 39 of 982
REJ09B0023-0400
Section 2 CPU