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Table 25.2 Recommended Values for Power-On/Off Sequence
Item
Time lag between VccQ and Vcc when turning on tpwu
Time lag between VccQ and Vcc when turning off tpwd
Unsettling operation time
Notes: 1. The figures shown above are recommended values, so they represent guidelines rather
than strict requirements.
2. The system design must, however, ensure that the undefined states of internal circuits
and pin states do not cause erroneous system operation.
3. The negative values in the maximum permissible value column indicate the allowed
difference in the time the voltages supplied as VccQ and Vcc take to rise. Therefore,
these figures do not allow the power supply in the reverse sequence: Vcc then VccQ.
4. When Vcc (1.8-V power) rises more quickly than VccQ (3.3-V power), the figure in the
maximum permissible value column is a negative value.
5. The time over which the internal state is undefined means time over which the first
supplying of power is in a transient state.
6. The pin states become defined when VccQ (min.) is reached. The power-on reset
(RESETP) is accepted after Vcc reaches Vcc (min.) and after the clock oscillation
settling time elapsed.
7. Ensure that the period over which the internal state is undefined is less than or equal to
100 ms.
Section 25 Electrical Characteristics
Symbol
Max. Permissible Value Unit
1
1
tunc
100
Rev. 4.00 Sep. 14, 2005 Page 909 of 982
ms
ms
ms
REJ09B0023-0400
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