Table 10.2 Interrupt Sources And Iprb To Iprj - Renesas HD6417641 Hardware Manual

Section 10 Interrupt Controller (INTC)

Table 10.2 Interrupt Sources and IPRB to IPRJ

Register Bits 15 to 12
IPRB WDT
IPRC IRQ3
IPRD IRQ7
IPRE Reserved*
IPRF ADC1
IPRG MTU0 (A/B/C/D)
IPRH MTU2 (A/B)
IPRI MTU4 (A/B/C/D)
IPRJ DMAC0
Note: Reserved: These bits are always read as 0. The write value should always be 0.
*
As shown in table 10.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit
groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0)
are set with values from H'0 (0000) to H'F (1111). Setting of H'0 means priority level 0 (masking
is requested); H'F means priority level 15 (the highest level).
Rev. 4.00 Sep. 14, 2005 Page 224 of 982
REJ09B0023-0400
Bits 11 to 8 Bits 7 to 4
Reserved* Reserved*
IRQ2 IRQ1
IRQ6 IRQ5
SCIF0 SCIF1
SCIF2 USB
MTU0 (V) MTU1 (A/B)
MTU2 (V/U) MTU3 (A/B/C/D)
MTU4 (V) POE
DMAC1 DMAC2
Bits 3 to 0
Reserved*
IRQ0
IRQ4
ADC0
CMT
MTU1 (V/U)
MTU3 (V)
IIC2
DMAC3