Renesas HD6417641 Hardware Manual page 295

Bit Bit Name
5 IDA1
4 IDA0
3 RWA1
2 RWA0
1 SZA1
0 SZA0
Initial
Value R/W Description
0 R/W Instruction Fetch/Data Access Select A
0 R/W Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
0 R/W Read/Write Select A
0 R/W Select the read cycle or write cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
0 R/W Operand Size Select A
0 R/W Select the operand size of the bus cycle for the
channel A break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Section 11 User Break Controller (UBC)
data access cycle
Rev. 4.00 Sep. 14, 2005 Page 245 of 982
REJ09B0023-0400