Figure 18.18 Cascaded Operation Setting Procedure; Figure 18.19 Example Of Cascaded Operation - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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Example of Cascaded Operation Setting Procedure: Figure 18.18 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
Start count
<Cascaded operation>
Examples of Cascaded Operation: Figure 18.19 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1 and phase counting mode has been
designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
TCNT_1
[1]
[2]

Figure 18.18 Cascaded Operation Setting Procedure

FFFD
FFFE
FFFF
0000

Figure 18.19 Example of Cascaded Operation

Section 18 Multi-Function Timer Pulse Unit (MTU)
[1]
Set bits TPSC2 to TPSC0 in the channel 1 TCR to
B'1111 to select TCNT_2 overflow/ underflow
counting.
[2]
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
0000
0001
0002
0001
Rev. 4.00 Sep. 14, 2005 Page 575 of 982
0001
0000
FFFF
0000
REJ09B0023-0400

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