Renesas HD6417641 Hardware Manual page 342

Section 12 Bus State Controller (BSC)
Bit Bit Name

5 to 2
1 HW1
0 HW0
• CS5AWCR
Bit Bit Name

31 to 19
18 WW2
17 WW1
16 WW0

15 to 13
Rev. 4.00 Sep. 14, 2005 Page 292 of 982
REJ09B0023-0400
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Delay Cycles from RD, WEn Negation to Address, CSn
0 R/W
Negation
0 R/W
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Number of Write Access Wait Cycles
0 R/W Specify the number of cycles that are necessary for
write access.
0 R/W
000: The same cycles as WR[3:0] setting (number of
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
read access wait cycles)