Burst Rom Read Cycle; Figure 25.22 Burst Rom Read Cycle (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
25.3.6

Burst ROM Read Cycle

CKIO
A25 to A0
CSn
RD/WR
RD
D31 to D0
WEn
BS
DACKn,
TENDn*
WAIT
Note: * Waveform for DACKn and TENDn when active low is selected.
(One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst)
Rev. 4.00 Sep. 14, 2005 Page 934 of 982
REJ09B0023-0400
T1 Tw
t
AD1
t t
CSD1 AS
t
RWD1
t
RSD
t t
BSD BSD
t
DACD
t
WTH1
t
WTS1
Figure 25.22 Burst ROM Read Cycle
Twx T2B
t
AD2
t
RDS3
t
WTH1
t
WTS1
Twb T2B
t t
AD2 AD1
t
CSD1
t
RWD1
t
RSD
t
RDH3
t
RDS3
t
DACD
t
RDH3