Renesas HD6417641 Hardware Manual page 333

Bit Bit Name
21 IWRRD2
20 WRRD1
19 IWRRD0
18 IWRRS2
17 IWRRS1
16 IWRRS0

15
Initial
Value R/W Description
1 R/W Idle Cycles for Read-Read in Another Space
1 R/W Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
1 R/W
space. The target cycle is a read-read cycle of which
continuous accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
1 R/W Idle Cycles for Read-Read in the Same Space
1 R/W Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
1 R/W
space. The target cycle is a read-read cycle of which
continuous accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 283 of 982
REJ09B0023-0400