Renesas HD6417641 Hardware Manual page 119

32-bit risc microcomputer superh risc engine family / sh7641 series
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Kinds of
Type
Instruction
Branch
9
instructions
System
14
control
instructions
Total:
67
Op Code
Function
BF
Conditional branch, delayed
conditional branch (T = 0)
BT
Conditional branch, delayed
conditional branch (T = 1)
BRA
Unconditional branch
BRAF
Unconditional branch
BSR
Branch to subroutine procedure
BSRF
Branch to subroutine procedure
JMP
Unconditional branch
JSR
Branch to subroutine procedure
RTS
Return from subroutine procedure
CLRT
T bit clear
CLRMAC
MAC register clear
CLRS
S bit clear
LDC
Load into control register
LDS
Load into system register
NOP
No operation
PREF
Data prefetch to cache
RTE
Return from exception handling
SETS
S bit setting
SETT
T bit setting
SLEEP
Transition to power-down mode
STC
Store from control register
STS
Store from system register
TRAPA
Trap exception handling
Rev. 4.00 Sep. 14, 2005 Page 69 of 982
REJ09B0023-0400
Section 2 CPU
Number of
Instructions
11
74
188

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