Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses In The Same Bank) - Renesas HD6417641 Hardware Manual

A25 to A0
A12/A11*
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
DACKn*

Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank)

Tnop Tc1
CKIO
1
CSn
BS
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 363 of 982
REJ09B0023-0400