Figure 25.27 Synchronous Dram Single Write Bus Cycle (Auto Precharge, Trwl = 1 Cycle) - Renesas HD6417641 Hardware Manual

CKIO
t
A25 to A0
t
1
A12/A11*
t
CSn
RD/WR
t
RASU/L
CASU/L
t
DQMxx
D31 to D0
BS
CKE
t
DACKn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.27 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRWL = 1 Cycle)
Tr Tc1
t t
AD1 AD1 AD1
Row
Column
address address
t t
AD1 AD1 AD1
WriteA
command
t
CSD1 CSD1
t t t
RWD1 RWD1 RWD1
t
RASD1
RASD1
t
t
CASD1
CASD1
t
DQMD1 DQMD1
t t
WDD2 WDH2
t t
BSD BSD
(High)
t
DACD DACD
Section 25 Electrical Characteristics
Trwl
Rev. 4.00 Sep. 14, 2005 Page 939 of 982
REJ09B0023-0400