Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses In The Same Bank, Cas Latency 1) - Renesas HD6417641 Hardware Manual

Tp
CKIO
A25 to A0
1
A12/A11*
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
(Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1)
Tpw Tr Tc1
Figure 12.25 Burst Read Timing
Section 12 Bus State Controller (BSC)
Td1 Td2 Td3
Tc2 Tc3 Tc4
Rev. 4.00 Sep. 14, 2005 Page 361 of 982
Td4
Tde
REJ09B0023-0400