Table 2.4 Dsr Register Bits - Renesas HD6417641 Hardware Manual

Table 2.4 DSR Register Bits
Bits Name (Abbreviation)
31 to 8 Reserved bits
7 Signed Greater Than bit (GT)
6 Zero bit (Z)
5 Negative bit (N)
4 Overflow bit (V)
3 to 1 Condition Select bits (CS)
0 DSP Condition bit (DC)
Note: After execution of a PADDC/PSUBC instruction, the DC bit sets the status of the operation
result in carry/borrow mode regardless of the CS bits.
Function
0: Always read as 0; always use 0 as the write value
Indicates that the operation result is positive (except 0),
or that operand 1 is greater than operand 2
1: Operation result is positive, or operand 1 is greater
than operand 2
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or operands are equal
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is smaller
than operand 2
Indicates that the operation result has overflowed
1: Operation result has overflowed
Designate the mode for selecting the operation result
status to be set in the DC bit
Do not set these bits to 110 or 111
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed greater than or equal to mode
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status has not occurred (false)
1: Designated mode status has occurred
Rev. 4.00 Sep. 14, 2005 Page 41 of 982
Section 2 CPU
REJ09B0023-0400