Figure 12.20 Basic Timing For Single Read (Cas Latency 1, Auto Pre-Charge) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
Single Read: A read access ends in one cycle when data exists in non-cacheable region and the
data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous
DRAM burst read/single write mode, only the required data is output.
Figure 12.20 shows the single read basic timing.
A25 to A0
A12/A11*
RASL, RASU
CASL, CASU
D31 to D0
DACKn*

Figure 12.20 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge)

Rev. 4.00 Sep. 14, 2005 Page 354 of 982
REJ09B0023-0400
Tr
CKIO
1
CSn
RD/WR
DQMxx
BS
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tc1 Td1 Tde Tap