Usbfifo Clear Register (Usbfclr) - Renesas HD6417641 Hardware Manual

Bit Bit Name
4 EP2DE

3 to 1
0 EP0iDE

20.3.19 USBFIFO Clear Register (USBFCLR)

USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all
the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not
clear a FIFO buffer during transmission/reception.
USBFCLR can be initialized to H'00 by a power-on reset.
Bit Bit Name

7
6 EP3CLR
5 EP1CLR
4 EP2CLR

3, 2
1 EP0oCLR
Initial
Value R/W Description
0 R EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data
All 0 R Reserved
The write value should always be 0.
0 R EP0i Data Present
This bit is set when the endpoint 0 transmit FIFO
buffer contains valid data.
Initial
Value R/W Description

0 Reserved
The write value should always be 0.
0 W EP3 Clear
When 1 is written to this bit, the endpoint 3 transmit
FIFO buffer is initialized.
0 W EP1 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 1 receive FIFO buffer are initialized.
0 W EP2 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 2 transmit FIFO buffer are initialized.

All 0 Reserved
The write value should always be 0.
0 W EP0o Clear
When 1 is written to this bit, the endpoint 0 receive
FIFO buffer is initialized.
Section 20 USB Function Module
Rev. 4.00 Sep. 14, 2005 Page 761 of 982
REJ09B0023-0400