Renesas HD6417641 Hardware Manual page 727

Bit Bit Name

11 to 9
8 PIE
7 POE3M1
6 POE3M0
5 POE2M1
4 POE2M0
Initial
value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Port Interrupt Enable
This bit enables/disables interrupt requests when any
of the POE0F to POE3F bits of the ICSR1 are set to 1
0: Interrupt requests disabled
1: Interrupt requests enabled
0 R/W POE3 mode 1, 0
These bits select the input mode of the POE3 pin.
0 R/W
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been
10: Accept request when POE3 input has been
11: Accept request when POE3 input has been
0 R/W POE2 mode 1, 0
These bits select the input mode of the POE2 pin.
0 R/W
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been
10: Accept request when POE2 input has been
11: Accept request when POE2 input has been
Section 18 Multi-Function Timer Pulse Unit (MTU)
sampled for 16 Pφ/8 clock pulses, and all are low
level.
sampled for 16 Pφ/16 clock pulses, and all are
low level.
sampled for 16 Pφ/128 clock pulses, and all are
low level.
sampled for 16 Pφ/8 clock pulses, and all are low
level.
sampled for 16 Pφ/16 clock pulses, and all are
low level.
sampled for 16 Pφ/128 clock pulses, and all are
low level.
Rev. 4.00 Sep. 14, 2005 Page 677 of 982
REJ09B0023-0400