Figure 18.32 Block Diagram Of Channels 3 And 4 In Complementary Pwm Mode - Renesas HD6417641 Hardware Manual

TDDR
Comparator
TCNT_3
Comparator
TGRD_3 TGRC_4

Figure 18.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode

TGRC_3 TCBR
TGRA_3 TCDR
TCNTS TCNT_4
TGRD_4
: Registers that can always be read or written from the CPU
: Registers that can be read or written from the CPU
(but for which access disabling can be set by port E)
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
Section 18 Multi-Function Timer Pulse Unit (MTU)
Match
signal
Match
signal
External cutoff
interrupt
Rev. 4.00 Sep. 14, 2005 Page 593 of 982
PWM cycle
output
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
External cutoff
input
POE0
POE1
POE2
POE3
REJ09B0023-0400