Renesas HD6417641 Hardware Manual page 118

Section 2 CPU
Kinds of
Type Instruction
Arithmetic 21
operation
instructions
Logic 6
operation
instructions
Shift 12
instructions
Rev. 4.00 Sep. 14, 2005 Page 68 of 982
REJ09B0023-0400
Op Code Function
MUL Double-precision multiplication
(32 × 32 bits)
Signed multiplication (16 × 16 bits)
MULS
Unsigned multiplication (16 × 16 bits)
MULU
NEG Sign inversion
NEGC Sign inversion with borrow
SUB Binary subtraction
SUBC Binary subtraction with carry
SUBV Binary subtraction with underflow
AND Logical AND
NOT Bit inversion
OR Logical OR
TAS Memory test and bit setting
TST Logical AND and T bit setting
XOR Exclusive logical OR
ROTL 1-bit left rotation
ROTR 1-bit right rotation
ROTCL 1-bit left rotation with T bit
ROTCR 1-bit right rotation with T bit
SHAL Arithmetic 1-bit left shift
SHAR Arithmetic 1-bit right shift
SHLL Logical 1-bit left shift
SHLLn Logical n-bit left shift
SHLR Logical 1-bit right shift
SHLRn Logical n-bit right shift
SHAD Arithmetic dynamic shift
SHLD Logical dynamic shift
Number of
Instructions
34
14
16