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Section 4 Clock Pulse Generator (CPG)
Bit
Bit Name
11, 10
9
STC1
8
STC0
7, 6
5
IFC1
4
IFC0
3, 2
1
PFC1
0
PFC0
Rev. 4.00 Sep. 14, 2005 Page 150 of 982
REJ09B0023-0400
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W
Frequency multiplication ratio of PLL circuit 1
00: × 1 time
0
R/W
01: × 2 times
10: × 3 times
11: × 4 times
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W
Internal Clock Frequency Division Ratio
0
R/W
These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
R/W
Peripheral Clock Frequency Division Ratio
1
R/W
These bits specify the division ratio of the peripheral
clock frequency with respect to the output frequency
of PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time
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