Renesas HD6417641 Hardware Manual page 753

Bit Bit Name
4 BRK
3 FER
Section 19 Serial Communication Interface with FIFO (SCIF)
Initial
value R/W Description
0 R/(W)* Break Detection
Indicates that a break signal has been detected in
receive data.
0: No break signal received
[Clearing conditions]
•
•
1: Break signal received*
[Setting condition]
•
Note: * When a break is detected, transfer of the
0 R Framing Error
Indicates a framing error in the data read from the
next receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive framing error occurred in the next data
[Clearing conditions]
•
•
1: A receive framing error occurred in the next data
[Setting condition]
•
BRK is cleared to 0 when the chip is a power-on
reset
BRK is cleared to 0 when software reads BRK
after it has been set to 1, then writes 0 to BRK
BRK is set to 1 when data including a framing
error is received, and a framing error occurs with
space 0 in the subsequent receive data
receive data (H'00) to SCFRDR stops after
detection. When the break ends and the
receive signal becomes mark 1, the transfer
of receive data resumes.
read from SCFRDR
FER is cleared to 0 when the chip undergoes a
power-on reset
FER is cleared to 0 when no framing error is
present in the next data read from SCFRDR
read from SCFRDR.
FER is set to 1 when a framing error is present in
the next data read from SCFRDR
Rev. 4.00 Sep. 14, 2005 Page 703 of 982
REJ09B0023-0400