Channel Priority - Renesas HD6417641 Hardware Manual

CHCR DMARS
RS[3:0] MID RID
1000
101010 00
110000 00
110010 00
110100 00
111010 00
101000 00
01
101100 00
111100 00
13.4.3

Channel Priority

When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. The four modes (fixed mode 1, fixed mode 2,
channel selective round-robin mode, and all-channel round-robin mode) are selected using the
priority bits PR0, PR1, and RC0 to RC3 in the DMA operation register (DMAOR).
Fixed Mode: In these modes, the priority levels among the channels remain fixed. There are two
kinds of fixed modes as follows:
Fixed mode 1: CH0 > CH1 > CH2 > CH3
Fixed mode 2: CH0 > CH2 > CH3 > CH1
DMA
Transfer
Request DMA Transfer
Source Request Signal
MTU0 TGI0A
(input capture interrupt/
compare match interrupt)
MTU1 TGI1A
(input capture interrupt/
compare match interrupt)
MTU2 TGI2A
(input capture interrupt/
compare match interrupt)
MTU3 TGI3A
(input capture interrupt/
compare match interrupt)
MTU4 TGI4A
(input capture interrupt/
compare match interrupt)
USB transmitter EP2FIFO empty transfer
request
USB EP1FIFO full transfer
receiver request
A/D converter 1 ADI (A/D conversion
end interrupt)
CMT1 Compare-match transfer
request
Section 13 Direct Memory Access Controller (DMAC)
Source
Any
Any
Any
Any
Any
Any
USBEPDR1 Any
ADDR1
Any
Rev. 4.00 Sep. 14, 2005 Page 429 of 982
Desti-
nation Bus Mode
Any Burst/
cycle steal
Any Burst/
cycle steal
Any Burst/
cycle steal
Any Burst/
cycle steal
Any Burst/
cycle steal
USBEPDR2 Cycle steal
Cycle steal
Any Cycle steal
Any Burst/
cycle steal
REJ09B0023-0400