Figure 12.24 Burst Read Timing (Bank Active, Same Row Addresses In The Same Bank, Cas Latency 1) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*
(Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1)
Rev. 4.00 Sep. 14, 2005 Page 360 of 982
REJ09B0023-0400
Tnop Tc1
1
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.24 Burst Read Timing
Td1 Td2 Td3
Tc2 Tc3 Tc4
Td4
Tde