Renesas HD6417641 Hardware Manual page 69

Classification
Clock
Operating mode
control
System control
Interrupts
Address bus
Data bus
Bus control
Symbol I/O
CKIO O
CKIO2 O
MD3, MD2, I
MD0
RESETP
I
RESETM
I
STATUS1, O
STATUS0
BREQ
I
BACK
O
NMI
I
IRQ7 to IRQ0 I
A25 to A0 O
D31 to D0 I/O
CS0,
O
CS2 to CS4,
CS5A, CS5B,
CS6A, CS6B
RD
O
Name Function
System clock Supplies the system clock to external
devices.
System clock Supplies the system clock to external
devices.
Mode set Sets the operating mode. Do not
change values on these pins during
operation.
MD2, MD0 set the clock mode, MD3
set the bus-width mode of area 0.
Power-on reset When low, this LSI enters the power-
on reset state.
Manual reset When low, this LSI enters the
manual reset state.
Status output Indicate that this LSI is in software
standby, reset, or sleep mode.
Bus-mastership Low when an external device
request requests the release of the bus
mastership.
Bus-mastership Indicates that the bus mastership
request has been released to an external
device. Reception of the BACK
acknowledge
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Non-maskable Non-maskable interrupt request pin.
interrupt Fix to high level when not in use.
Interrupt requests Maskable interrupt request pin.
7 to 0 Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
Address bus Outputs addresses.
Data bus 32-bit bidirectional bus.
Chip select 0, Chip-select signal for external
2 to 4, 5A, 5B, memory or devices.
6A, 6B
Read Indicates reading of data from
external devices.
Rev. 4.00 Sep. 14, 2005 Page 19 of 982
Section 1 Overview
REJ09B0023-0400