Table 12.8 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (1)-2 - Renesas HD6417641 Hardware Manual

Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(1)-2
BSZ A2/3
1, 0 ROW
1, 0
11 (32 bits) 00 (11 bits)
Output Pin of Row Address
This LSI Output Cycle
A17 A25
A16 A24
A15 A23*
A14 A22*
A13 A21
A12 A20*
A11 A19
A10 A18
A9 A17
A8 A16
A7 A15
A6 A14
A5 A13
A4 A12
A3 A11
A2 A10
A1 A9
A0 A8
Example of connected memory
128-Mbit product (1 Mword × 32 bits × 4 banks, column 8 bits product): 1
64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Setting
A2/3
COL
1, 0
00 (8 bits)
Column Address
Output Cycle
A17
A16
2 2
A23*
2 2
A22*
A13
2 1
L/H*
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Section 12 Bus State Controller (BSC)
SDRAM Pin
A13 (BA1)
A12 (BA0)
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Rev. 4.00 Sep. 14, 2005 Page 341 of 982
Function
Unused
Specifies bank
Specifies
address/precharge
Address
Unused
REJ09B0023-0400