Table 12.9 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (2)-1 - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(2)-1
BSZ A2/3
1, 0 ROW
1, 0
11 (32 bits) 00 (11 bits)
Output Pin of Row Address
This LSI Output Cycle
A17 A26
A16 A25
A15 A24*
A14 A23*
A13 A22
A12 A21
A11 A20*
A10 A19
A9 A18
A8 A17
A7 A16
A6 A15
A5 A14
A4 A13
A3 A12
A2 A11
A1 A10
A0 A9
Example of connected memory
256-Mbit product (2 Mwords × 32 bits × 4 banks, column 9 bits product): 1
128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.
Rev. 4.00 Sep. 14, 2005 Page 342 of 982
REJ09B0023-0400
Setting
A2/3
COL
1, 0
00 (8 bits)
Column Address
Output Cycle
A17
A16
2 2
A24*
2 2
A23*
A13
1
L/H*
2
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDRAM Pin
A13 (BA1)
A12 (BA0)
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
Unused
Specifies bank
Address
Specifies
address/precharge
Address
Unused