C Bus Interface; Figure 16.1 Block Diagram Of I - Renesas HD6417641 Hardware Manual

2
Section 16 I C Bus Interface 2 (IIC2)
SCL
SDA
[Legend]
2
ICCR1 : I C bus control register 1
2
ICCR2 : I C bus control register 2
2
I C bus mode register
ICMR :
2
ICSR : I C bus status register
2
ICIER : I C bus interrupt enable register
2
ICDRT : I C bus transmit data register
2
ICDRR : I C bus receive data register
2
I C bus shift register
ICDRS :
SAR : Slave address register
NF2CYC: NF2CYC register
Rev. 4.00 Sep. 14, 2005 Page 474 of 982
REJ09B0023-0400
Output
control
Noise canceler
Output
control
Noise canceler
Bus state
decision circuit
Arbitration
decision circuit

Figure 16.1 Block Diagram of I

Transmission/
reception
control circuit
ICDRT
ICDRS
ICDRR
NF2CYC
ICIER
2

C Bus Interface 2

Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Address
comparator
ICSR
Interrupt
Interrupt
generator
request