Table of Contents
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Section 1 Overview
Items
DSP
Clock pulse
generator (CPG)
Watchdog timer
Rev. 4.00 Sep. 14, 2005 Page 2 of 828
REJ09B0023-0400
Specification
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Mixture of 16-bit and 32-bit instructions
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32-/40-bit internal data paths
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Multiplier, ALU, barrel shifter and DSP register
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Large DSP data registers
Six 32-bit data registers
Two 40-bit data registers
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Extended Harvard Architecture for DSP data bus
Two data buses
One instruction bus
•
Max. four parallel operations: ALU, multiply, and two load or store
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Two addressing units to generate addresses for two memory access
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DSP data addressing modes: increment, indexing (with or without
modulo addressing)
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Zero-overhead repeat loop control
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Conditional execution instructions
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Clock mode: Input clock can be selected from external input (EXTAL
or CKIO) or crystal oscillator
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Three types of clocks generated:
CPU clock: maximum 100 MHz
Bus clock: maximum 50 MHz
Peripheral clock: maximum 33 MHz
•
Power-down modes:
Sleep mode
Standby mode
Module standby mode
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Three types of clock modes (selectable PLL2 × 2 / × 4, clock / crystal
oscillator)
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On-chip one-channel watchdog timer
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Select from operation in watchdog-timer or interval-timer mode.
•
Interrupt generation is supported for the interval-timer mode.
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