Interrupt Control Register 3 (Icr3) - Renesas HD6417641 Hardware Manual

10.3.4

Interrupt Control Register 3 (ICR3)

ICR3 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7
and IRQ6 individually: rising edge, falling edge, high level, or low level. This register is
initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit Bit Name

15 to 4
3 IRQ71S
2 IRQ70S
1 IRQ61S
0 IRQ60S
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0 R/W IRQn Sense Select
0 R/W These bits select whether interrupt request signals
corresponding to pins IRQ7 and IRQ6 are detected by
0 R/W
a rising edge, falling edge, high level, or low level.
0 R/W
Bit 2n+1 Bit 2n
IRQn1S IRQn0S
0
0
1
1
n = 6 and 7
Section 10 Interrupt Controller (INTC)
0 : Interrupt request is detected at the
falling edge of IRQn input
1 : Interrupt request is detected at the
rising edge of IRQn input
0 : Interrupt request is detected on low
level of IRQn input
1 : Interrupt request is detected on high
level of IRQn input
Rev. 4.00 Sep. 14, 2005 Page 227 of 982
REJ09B0023-0400