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BSC functional block diagram is shown in figure 12.1.
BACK
BREQ
WAIT
CS0, CS2, CS3,
CS4, CS5A, CS5B,
CS6A, CS6B
MD3
A25 to A0,
D31 to D0
BS, RD/WR,
RD, WE3 to WE0,
RASU, RASL,
CASU, CASL
CKE, DQMxx, AH,
FRAME
[Legend]
CMNCR:
Common control register
CSnWCR:
CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
RWTCNT:
Reset wait counter
CSnBCR:
CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
SDCR:
SDRAM control register
RTCSR:
Refresh timer control/status register
RTCNT:
Refresh timer counter
RTCOR:
Refresh time constant register
Bus
mastership
controller
Wait
controller
Area
controller
Memory
controller
Refresh
controller
Figure 12.1 BSC Functional Block Diagram
Section 12 Bus State Controller (BSC)
CMNCR
CS0WCR
CS6BWCR
RWTCNT
CS0BCR
CS6BBCR
SDCR
RTCSR
RTCNT
Comparator
RTCOR
BSC
Rev. 4.00 Sep. 14, 2005 Page 271 of 982
REJ09B0023-0400
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