Ep3 Interrupt-In Transfer; Figure 20.12 Ep3 Interrupt-In Transfer Operation - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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Section 20 USB Function Module
20.4.6

EP3 Interrupt-IN Transfer

IN token reception
Data transmission to host
Set EP3 transmission
(USBIFR1/EP3 TS = 1)
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
operation flow in which, if there is data to be transferred, the EP3 DE bit in the USB data status register
is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Rev. 4.00 Sep. 14, 2005 Page 778 of 982
REJ09B0023-0400
USB function
No
Valid data
in EP3 FIFO?
NACK
Yes
ACK
Interrupt request
complete flag

Figure 20.12 EP3 Interrupt-IN Transfer Operation

Application
Is there data
for transmission
to host?
Yes
Write data to USBEP3 data
register (USBEPDR3)
Write 1 to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
Clear EP3 transmission
complete flag
(USBIFR1/EP3 TS = 0)
Is there data
for transmission
to host?
Yes
Write data to USBEP3 data
register (USBEPDR3)
Write 1 to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
No
No

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