Renesas HD6417641 Hardware Manual page 177

In figure 3.18, exceptions generated by instructions marked as B and C are handled as follows:
• Interrupt and DMA address errors
An exception is accepted at neither instruction B or C, and the request is not even saved. A
request is detected for the first time and accepted when the next instruction A is executed.
Interrupts and DMA address errors are not accepted during a repeat loop with four or less
instructions, as shown in 1 to 4 in figure 3.18.
• User break before execution
An exception is accepted at instruction B, and the address of instruction B is stored into SPC.
An exception is not accepted at instruction C, but the request is saved, and is accepted just
before the next instruction A or B is to be executed. The address of this next instruction A or B
is stored into SPC.
• User break after execution
An exception is accepted at neither instruction B nor C, but the request is saved, and is
accepted just before the next instruction A or B is to be executed. The address of this next
instruction A or B is stored into SPC.
• CPU address error
When a CPU address error occurs by execution of instruction B or C, the exception is
accepted, but the value stored into SPC is not the address of the instruction at where the
exception occurred. Therefore, return from the exception handler routine cannot be performed
correctly. In this case, H'070 is set in EXPEVT as the exception code (also see section 9,
Exception Handling). To finish the repeat loop correctly, a CPU error must not be generated at
instruction B or C.
Exception Type
Interrupt
DMA address error
UDI break
User break before execution
User break after execution
CPU address error
Instruction B
Not accepted
Not accepted
Not accepted
Not accepted
Not accepted
Accepted as exception code H'070
Section 3 DSP Operation
Instruction C
Not accepted
Not accepted
Not accepted
Not accepted
Not accepted
Accepted as exception code H'070
Rev. 4.00 Sep. 14, 2005 Page 127 of 982
REJ09B0023-0400